Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning - YouTube
SiFive VIU75 Accelerates Vector Math - AB Open
RISC-V Vector Extension
NeuralScale: Industry Leading General Purpose Programmable NPU Architecture based on RISC-V - RISC-V International
RISC-V
A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Specialized Accelerators Enable Vector Processing on RISC-V - EE Times India
Tutorial: RISC-V Vector Extension Demystified - 2020 RISC-V Summit - YouTube
SiFive reveals X280 core and AndeSight RISC-V IDE moves to v5.0
RISC-V Vector Extension in a Nutshell (Part 4): permute operations : r/asm
![PDF] RISC-V2: A Scalable RISC-V Vector Processor | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/d913144ed53fb893b4ac31d2c1022d0f70d90eb3/2-Figure1-1.png "PDF] RISC-V2: A Scalable RISC-V Vector Processor | Semantic Scholar")
PDF] RISC-V2: A Scalable RISC-V Vector Processor | Semantic Scholar
GEMM based on the RISC-V Vector Extension (Part 2) | Luffca
SiFive VIU75 Accelerates Vector Math - AB Open
RISC-V - Wikipedia
SiFive's brand-new P550 is one of the world's fastest RISC-V CPUs | Ars Technica
What is the RISC-V ecosystem?
RISC-V Vector Extension Webinar I
64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
Enhancing RISC-V Vector Extensions to Accelerate... - SemiWiki
64-bit CPU with RISC-V Vector Extension
NSITEXE teams for RISC-V edge AI platform ...
Vector Extension 0.7 - YouTube
Vector Accelerator for RISC-V architecture - Diglab
OGAWA, Tadashi on Twitter: "=> "RISC-V Vector Extension proposal", Roger Espasa, Esperanto Technologies, 7th RISC-V WS, Nov 29 2017 https://t.co/zOAtigcZf3 https://t.co/94rSjjvP9J 32x (32bit, MVL=8 + 16bit) D. Ditzel, Esperanto Technologies, Nov 28
